HiPEAC · High Performance and Embedded Architecture and Compilation

Due to technology limitations, the domain of high-performance processors is experiencing a radical shift towards parallelism through on-chip multi-cores and chip customization leading to heterogeneous multi-core systems. Furthermore, the commodity market, the supercomputing market and the embedded market are increasingly sharing the same challenges, leading to convergence of the three markets.<br/><br/>The main challenges for the future high-performance embedded systems have been documented in the HiPEAC roadmap (http://www.HiPEAC.net/roadmap), which forms the basis of the HiPEAC strategic research agenda. <br/><br/>The goal of the HiPEAC Network of Excellence is (i) to join forces in Europe to collectively work on the HiPEAC strategic research agenda, (ii) to realize European excellence in computing architectures, system software and platforms to enable the development of new applications, and (iii) to allow European companies to achieve world-leading positions in computing solutions and products.<br/><br/>In order to reach that goal, HiPEAC (a) will stimulate mobility between partners (internships, sabbaticals, research visits, cluster meeting), (b) will coordinate and steer research in 9 research clusters: (i) Multi-core architecture, (ii) Programming models and operating systems, (iii) Adaptive compilation, (iv) Interconnects, (v) Reconfigurable computing, (vi) Design methodology and tools, (vii) Binary translation and virtualization, (viii) Simulation platform, (ix) Compilation platform, and (c) will spread excellence by running the HiPEAC conference, the ACACES summer school, the HiPEAC journal, a newsletter, a website, seminars, technical reports, workshops, and awards.<br/><br/>This program of activities will lead to the permanent creation of a solid and integrated virtual centre of excellence consisting of several highly visible departments, and this virtual centre of excellence will have the necessary critical mass to really make a difference for the future of computing systems i